1. Field of the Invention
The present invention relates in general to a sense amplifier for a semiconductor memory device for sense-amplifying data signals, transferred from memory cells to bit lines, and more particularly, to a sense amplifier for a semiconductor memory device which is capable of minimizing a noise component being generated and enhancing the operating speed of the semiconductor memory device.
2. Description of the Prior Art
In a semiconductor memory device, generally, a sense amplifier is adapted to sense-amplify data signals with a swing width of several tens mV, transferred from memory cells to bit lines, in such a manner that the data signals can have a swing width from a ground voltage to a supply voltage. The bit lines have an extended length because a plurality of memory cells are connected thereto such an extended length allows the bit lines to have a desired impedance. The sense amplifier is degraded in operating speed when the supply voltage is reduced in level, since it consumes at least 30% of an operating current and drives the bit lines. On the other hand, when the supply voltage is increased in level, the sense amplifier is normal in operating speed, but it generates a high noise signal on the data signals, the ground voltage and the supply voltage. Such problems appear more significantly in a refresh mode in which the plurality of memory cells are simultaneously driven. The above problems with the sense amplifier for the semiconductor memory device will hereinafter be described in detail with reference to FIG. 1.
Referring to FIG. 1, there is shown a circuit diagram of a conventional sense amplifier for a semiconductor memory device. As shown in this drawing, the conventional sense amplifier comprises two PMOS transistors MP2 and MP3 and two NMOS transistors MN2 and MP3 connected between true and complementary bit lines BL and/BL to form a cross coupled latch. The sense amplifier further comprises a PMOS transistor MP1 for transferring a supply voltage from a supply voltage source Vcc to the cross coupled latch in response to a first sense amplifier control signal .phi.SEP supplied thereto through an inverter G1, and an NMOS transistor MN1 for transferring a ground voltage from a ground voltage source vss to the cross coupled latch in response to a second sense amplifier control signal .phi.SEN supplied thereto through an inverter G2. Each of capacitors C.sub.BL and C.sub./BL is connected to a corresponding one of the true and complementary bit lines BL and/SL by a dotted line to model a parasitic capacitance of the corresponding bit line.
The true and complementary bit lines BL and/BL are supplied with true and complementary data signals from memory cells, the data signals having a potential difference of several tens mV. When the first sense amplifier control signal .phi.SEP inverted by the inverter G1 goes low in logic, the PMOS transistor MP1 is turned on to transfer the supply voltage from the supply voltage source Vcc to the cross coupled latch. When the second sense amplifier control signal .phi.SEN inverted by the inverter G2 goes high in logic, the NMOS transistor MN1 is turned on to transfer the ground voltage from the ground voltage source Vss to the cross coupled latch. The cross coupled latch sense-amplifies the true and complementary data signals on the true and complementary bit lines BL and/BL according to a difference Vcc-Vss between the supply voltage Vcc and the ground voltage vss by the PMOS transistor MP1 and the NMOS transistor MN1. Noticeably, the PMOS transistor MP1 and the NMOS transistor MN1 transfer the voltage difference Vcc-Vss directly to the cross coupled latch in response to the first and second sense amplifier control signals .phi.SEP and .phi.SEN regardless of the level of the voltage difference Vcc-Vss. For this reason, in the case where the voltage difference Vcc-Vss is high in level, the cross coupled latch generates a relatively high noise component on the true and complementary data signals, the ground voltage Vss and the supply voltage Vcc. In the case where the voltage difference Vcc-Vss is low in level, The cross coupled latch sense-amplifies the True and complementary data signals at a relatively low speed. The generation of the noise component and the degradation in the operating speed appear more significantly in a refresh mode in which 1K to 4K memory cells are simultaneously driven.